The conventional host device communicates with the memory card using a half duplex communication protocol to perform directional transfers alternately. In other words, at a time, one pathway can transfers information in one direction. During half duplex communication protocol, the pathway should change transfer direction frequently by switching the direction of the pathway. In conventional half duplex communication, the direction of the pathway is changed by detecting a signal edge to perform switch, i.e., if the signal is changed from a low level to a high level, the transfer direction of the pathway is triggered to switch. Disadvantageously, the conventional method of switching the direction of the pathway is reasonable for the low speed half duplex communication and is not applicable for high speed communication. Also, it is difficult and expensive to solve the problems in high speed communication, and the interface circuit of the timing cannot be required.
FIG. 1 shows a conventional interface circuit 104 for a host device 102 to communicate with a memory card 106 in a legacy mode, for example a secure digital (SD) card, a universal flash storage (UFS) card, multimedia card (MMC), where the host device 102, the interface circuit 104 and the memory card 106 compose a signal transmission system 100. Specifically, the host device 102 can operates on the memory card 106 with many kinds of mode via the interface circuit 104, for example, reads data from or writes data to the memory card 106. As shown in FIG. 1, the interface circuit 104 includes a input mode 1041 for receiving signals from the host device 102, and sending the signal to a signal edge detection module 1043, the signal transferred from the host device 102 to the interface circuit 104 includes, but is not limited to, a clock signal, a command signal or a data signal. The signal edge detection module 1043 detects if the signal has a change, for example, the signal is changed from a high level to a low level or from a low level to a high level. When the signal edge detection module 1043 detects changes from the signal, the interface circuit 104 turns on the pathway between the host device 102 and the memory card 106, i.e., the signal is transferred to the memory card 106 via an output module 1045. On the contrary, when the memory card 106 sends signal to the host device 106, such as the host device 106 reads data signal on the memory card 106, the input module 1042 receives the data signal from the memory card, and sends the data signal to signal edge detection module 1044 for detecting. It should be understood that the framing and function of signal edge detection module 1044 is same as the signal edge detection module 1043. By the way of an example, when the signal edge detection module 1044 detects changes of the signal from the memory card 106, the interface circuit 104 turns on the pathway between the host device 102 and the memory card 106, i.e., the signal is transferred from the memory card 106 to the host device 102 via an output module 1046.
As described above, During the host device 102 communicates with the memory card 106 via the interface circuit 104, if the host device 102 communicates with the memory card 106 in a high speed mode, the signal edge detection module 1043 and/or the signal edge detection module 1044 need to detect the changes of the signal by using a higher speed detecting circuit which increases the design cost of the interface circuit. Moreover, the conventional interface circuit 104 has shortcomings of poor anti-noise. As the signal passes each module in the interface circuit 104 which will create data transmission delay, and the signal may not be sampled correctly. For example, when the signal transfers from one end to another end (i.e., from host device to the memory card), the signal may delay differently in each module, it may causes that the length of the effective sampling window is very short and cannot satisfy the timing requirements, then the signal cannot be sampled correctly. Lastly, the timing requirement is not same during the memory card 106 works in a different mode. The conventional interface circuit 104 cannot adjust the timing to satisfy the timing requirement when in all kinds of modes. So, an interface circuit can satisfy timing requirements when the host device communicates with the memory card in all kinds of mode is necessary.